The present invention is generally directed to a system and method for level translation in a serial data interface. More specifically, the present invention is directed to a system and method for providing voltage level translation in a serial data interface with minimal signal attenuation and bandwidth reduction. The subject system and method provide for translation of common mode voltage to enable safe differential serial data transfer between integrated circuits, even in high speed environments, without adverse effect upon the transferred signal.
With the many advances in the electronics industry, high speed differential serial data transfer between integrated circuits has become commonplace. Many of those same advances, however, require ever more stringent control over various operational parameters, not the least of which is the level of common mode voltage that certain low voltage devices may safely tolerate. Sensitivities to common mode voltage, the average voltage level of differentially paired signals, have heightened considerably with semiconductor processing technologies increasingly yielding thinner oxide devices.
Serial communication involves the process of sending data one bit at a time sequentially, over a communication channel or computer bus. Among other things, serial interfaces minimize the number of input/output pins on integrated circuits (IC's) and reduce the wiring interconnects required, thereby decreasing the cost of IC's. Examples of such low-cost serial interfaces used to reduce the number of pins in IC's, include SPI, I2C, and 1-Wire links.
A number of standards have been generated over the years to define data rates and signal levels carried by these serial links (buses). Such serial interface standards require DC coupling between integrated circuits to allow for indeterminately long strings of 1's and 0's. Notably, some of the standards reflect earlier technologies requiring higher supply voltages (for example, 1.8V, 2.5V, or 3.3V) than may be acceptable for certain technologies today. The thinner oxide transistor devices available now, especially for high speed applications, offer gate oxide thickness in the 90 nm, 65 nm, 45 nm range and below. These devices can safely tolerate common mode voltages Vcm up to about 1 V, which is significantly less than the Vcm levels in signals generated by earlier integrated circuit technologies. Interface measures are necessary to ensure that the Vcm levels applied to receiving circuits containing such thin oxide transistor devices are translated to sufficiently low levels that they do not cause harm.
Several approaches have been taken in the industry to address this problem of common mode voltage incompatibility. One often used approach is the inclusion of an AC coupling capacitor in each differential signal line, so that the non-varying portion of an incoming signal on the line is filtered out. An obvious drawback of this approach is that the coupling capacitors prevent the passage of DC voltage levels. An additional drawback is that it requires at least two external components for each pair of differential serial lines. Since the number of serial lines on an integrated circuit may be quite high, the number of external components may also become quite high, excessively so.
Another known approach to addressing the problem of common mode voltage incompatibility is to include in the receiver integrated circuit an input stage containing thicker oxide transistors having higher voltage tolerance. Such high voltage transistors, however, tend to be considerably slower than the thinner oxide transistors required for high speed applications. Receiver circuits integrated with these higher voltage input stages may not even operate when their serial buses receive very high speed data streams in the range, for instance, of 10 Gbit/sec. An additional drawback of this approach is that receiver circuits with the thicker oxide transistors are powered by higher supply voltages which lead to greater power dissipation.
Yet another known approach to addressing the common mode voltage incompatibility problem is to level shift the incoming signal toward ground using resistive means. This, however, adds undue power dissipation by the resistive elements. Another drawback is the bandwidth reduction due to the resistive elements interacting with the parasitics of the given load capacitance. Furthermore, the shifted voltage for the incoming voltage is determined necessarily by the input common mode voltage and for that reason cannot be well controlled. Finally, the resistive level shifting of the incoming common mode voltage means that the desired signal level is necessarily attenuated at input (by the resistive elements' voltage divider ratio). Such signal attenuation is undesirable, especially in case of a long line, since the signal may already be greatly degraded as it is by the line channel.
There is therefore a need for an interface approach whereby compatibility between an incoming high level common mode voltage signal and a receiver stage with heightened sensitivity to such high voltage levels may be preserved, with minimal attenuation of the incoming signal and minimal reduction in signal bandwidth.